Sample rate conversion refers to changing a sampling rate of a discrete signal. When the sapling rate is increased, the process may also be referred to as upsampling, which involves interpolation of sample points of the original sampled signal. When the sapling rate is decreased the process may also be referred to as downsampling, which reduces the sample rate of the signal. Upsampling typically includes low pass filtering after increasing the data rate to smooth the signal, and downsampling typically includes low pass filtering before decreasing the data rate, to avoid aliasing distortion. Applications of sample rate conversion include, inter alia, image scaling and rate conversion of audio signals.
In a digital signal processors (DSP) with a register-based architecture, data is loaded into registers, computations are performed on the content of the registers, and results are transferred from the registers back to memory. When performing a computation, the execution unit will use several registers for storing source operands and write the results to a destination register. In a vector register these same rules hold true, except that the contents of the registers are partitioned into multiple elements or memory elements (based on the vector width), whereby each element may be manipulated independently of other elements.
Typically, implementing a sample rate converter in a DSP requires permuting and organizing the data. This is due to the fact that the sample rate converter performs rate conversion and therefore does not necessarily shift each data element by one for each sequential output sample. For example, when upsampling with a vector processor, the input data would need to be permuted in such a way to repeat the same input data according to a pattern.
Permutation of data elements for sample rate conversion requires dedicated hardware resources, including multiplexers and complex wiring for moving data elements between memory elements. Typically, permuting requires an additional pipeline stage, adding to the hardware complexity. Further, the permutation has to be reconfigured, for example by software, for each output sample. This consumes DSP resources, including memory operations and/or vector registers, which may increase programming effort and may also require extra DSP cycles, slowing the rate of the conversion and degrading the DSP performance.